(a) Field of the Invention
The present invention relates to a thin film transistor array panel.
(b) Description of the Related Art
Liquid crystal displays (LCDs) are among the most widely used flat panel displays. A typical LCD includes a pair of panels provided with field-generating electrodes, and a liquid crystal (LC) layer interposed therebetween. The LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the LC layer. This field orients the LC molecules, which polarizes incident light.
One widely employed LCD structure utilizes field generating electrodes respectively formed on two display panels. A plurality of pixel electrodes are arranged in a matrix format on one display panel, and one common electrode covers the surface of the other display panel. In the liquid crystal display, each pixel electrode is separately applied with a voltage to display images. A thin film transistor (TFT) is connected to each pixel electrode for switching the voltage applied to the pixel electrode, as well as a plurality of gate lines transmitting signals to control the thin film transistor, and a plurality of data lines transmitting the voltage that is applied to the pixel electrode.
The thin film transistor array panel is controlled by a driving circuit connected to the gate line and the data line. The driving circuit may be attached to the panel by a tape carrier package (TCP) type structure, or a chip-on-glass (COG) type structure. With the TCP type structure, a tape mounted with the driving chip is separately attached to the thin film transistor array panel, whereas with the COG type structure, the driving chip is directly mounted on an insulation substrate of the thin film transistor array panel. Conventionally, TCP type structures have been more widely used. However, the COG type structure has recently gained popularity due to its smaller footprint and lower cost. Also, TCP type structures typically require an additional circuit for applying signals to their driving circuits. This added circuit must be formed on an additional printed circuit board (PCB), and connected through an additional flexible printed circuit (FPC) film.
In COG type thin film transistor array panels, to easily confirm a defect in wiring when inspecting for defects, an identification number is given to each gate pad and each data pad (i.e., the pads connected to a gate driving chip and a data driving chip, respectively).
However, as components have become more highly integrated, the interval between the plurality of gate pads or the plurality of data pads has shrunk to the point that it is difficult to form these identification numbers.
When an identification number is not formed between the gate pads or the data pads, it is difficult to find and keep track of defective wiring. Also, if the identification number partially overlaps the gate pad and is formed with a different material from the gate pad, a step is generated at the overlap. This partial overlap is more likely to generate defects during pressing of bond wires onto the pads. One approach to overcoming this problem is to form small identification numbers in the narrow spaces between neighboring pads. However, these numbers are often too small to read easily, and also risk shorting their adjacent pads to each other.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention. Therefore, it may contain information not in the prior art and not already known to a person of ordinary skill in the art.